Commodore specification of the chip can be found at: http://www.classiccmp.org/cini/pdf/Commodore/ds_8701.pdf I took signal names and block diagram from this source as a starting point. Here is a description of what I discovered so far. Crystal oscillator ================== Pierce oscillator is used here with 2 capacitors (one external and one internal) and one resistor and 2 parallel inverting buffers. Crystal is of course external. - External capacitor at at XTLOUT (pin 13) and internal at XTLIN (pin 14). - There are totally 10 segments for that internal capacitor but only 8 is used. The area of this capacitor (8 segments) is 60699 um2 if I suppose 1 mm has 2646 pixels. - At each of the XTLOUT and XTLIN pins is small circuit made of capacitor (507 um2), resistor and transistor. Function of this is yet unknown to me, must simulate it in SPICE, but I think it could make the oscillator signal more rectangular. If we suppose that internal big capacitor at XTLIN has approximately the same capacity as external one at XTLOUT (i.e. ~18 pF) we can say that those 2 small capacitor have capacity of 18/60699*507 i.e. ~0.15 pF. - In previous revision There originally were 3 inverting buffers, now there are only 2, the last is still there but is inactivated. Color frequency output buffer ============================= The signal from XTLIN is double inverted and buffered and put on the COLOR pad. Frequency doubler and internal clock generator ============================================== The input to this part is inverted COLOR signal (/COLOR) and /PAL signal. /Color signal is inverted, delayed and recombined resulting in Phi1 and Phi2 signals. Phi1 and Phi2 have double frequency of the oscillator and are out of phase. - /COLOR is inverted (to C signal) and again inverted (to /C signal). - /C signal is delayed by 10 inverters (for NTSC) or by 6 inverters (for PAL) resulting in delayed signal /D. - There originally were 2 more inverters in PAL branch, but were made inactive in this revision. - /D is further inverted to D. - So we have original C and /C signals derived from COLOR signal and D and /D signals delayed by half a crystal clock. - Those for signals are and-or-inverted resulting with Phi1 and Phi2 signals. - Phi1=NOR(C*D,/C*/D) while Phi2=NOR(C*/D,/C*D) - Phi1 and Phi2 are again shaped by 2 inverters each and go thru NOR based R-S flip-flop to be sure that they do not overlap. Frequency divider ================= The input are Phi1, Phi2, /PAL and /RESET signals. The output are #0 PULSE and #3 PULSE (#0P and #3P respectively in the schematics). The frequency of those pulses is the frequency of oscillator divided by 3.5 for NTSC and by 4.5 for PAL. Or in fact it is frequency of Phi2 divided by 7 for NTSC and by 9 for PAL. Each pulse lasts one Phi2 cycle and #3P is delayed by 3 Phi2 cycles to #0P. - The divider consists of 4 bit shift register with outputs d0, d1, d2 and d3. Each bit is made of 2 inverters each of the separated by pass transistor driven by Phi1 and Phi2 signals respectively. - The input (signal Din) to the first bit of the shift register is inverted as the NOR gate creating the input is in place of the first inverter. - Din is NOR of DinA and DinB signals. - DinA is NOR from d0 to d3 signals steered by Phi2, thus its inputs are called d0_2 to d3_2. - DinB takes as output directly d1 to d3 signal and the result of whole XOR is steered by Phi2 and then passed to Din NOR. - When /RESET input is low the shift registers contains all zeroes and #0P and #3P signals are low all the time. - #0P and #3P are created by NOR of d0_2 to d3_2. The equations for Din, #0P and #3P signals are: DinA=NOR(PAL*d3_2,d2_2,NTSC*d1_2,d0_2) DinB=XOR(NTSC*d3,d2,PAL*d1)@Phi2 Din=NOR(DinA,DinB,RESET) #0P=NOR(PAL*d3_2,d2_2,d1_2,/d0_2) #3P=NOR(PAL*/d3_2,d2_2,/d1_2,/d0_2) Sor for NTSC and PAL we get after simplification: NTSC ---- DinA=NOR(d2,d1,d0) DinB=XOR(d2,d1) Din=NOR(DinA,DinB,RESET) #0P=NOR(d2,d1,/d0) #3P=NOR(d2,/d1,/d0) # |01234560 --+-------- d3|10010111 d2|00101110 d1|01011100 d0|10111001 d2|00001111 d1|00110011 d0|01010101 ----+-------- /Din|10111100 PAL --- DinA=NOR(d3,d2,d0) DinB=XOR(d3,d2) Din=NOR(DinA,DinB,RESET) #0P=NOR(d3,d2,d1,/d0) #3P=NOR(/d3,d2,d1,d0) # |0123456780 --+---------- d3|0001011110 d2|0010111100 d1|0101111000 d0|1011110001 d3|0000000011111111 d2|0000111100001111 d1|0011001100110011 d0|0101010101010101 ----+---------------- /Din|1010111111110000 Pulse shaper ============ To be done. Dot frequency output buffer =========================== To be done. Undocumented part of the chip producing unknown signals on pins 10 and 11 ========================================================================= To be done. Undocumented part of the chip near pin 1 ======================================== To be done.