Intel 8085 Instruction Decode ROM

Intel 8085 instruction decode ROM

In my layers drawing instruction decode ROM occupies rectangle from 5263,1866 to 5712,3117. In the table below the content of the ROM is shown. Every 1 means a FET which can pull each line down. The table is in the same sequence as it is in the real chip.
Particular line is high when instruction register contains corresponding instruction. Every line contains NOR term meaning default value is logical 1. The ROM has 18 inputs. Every bit of instruction register and its negation (INS_B0, /INS_B0 ... INS_B7, /INS_B7) and two additional signals used for decoding of M pseudoregister.
First is INS_M1 defined as NOR(/INS_B5,/INS_B4,INS_B3) i.e. is 1 for instructions xx110xxx and 0 otherwise. The second is INS_M2 and is defined as NOR(/INS_B2,/INS_B1,INS_B0) i.e. is 1 for instructions xxxxx110 and 0 otherwise.
Every pair of instruction bit and its negation can tell if corresponding bit should be 0, 1 or don't care. Note that there is no decode line for NOP instruction. The reason is that this instruction does not do anything specific.
Instruction register gets loaded during cycle M1, state T3, phase P1 and it is held there till M1, T2, P2 of the next instruction.
In the instruction list below ALU means all 8 ALU instructions (ADD, ADC, SUB, SBB, ANA, XRA, ORA, CMP) or their immediate version (ADI, ACI, SUI, SBI, ANI, XRI, ORI, CPI). String cc in Jcc, Ccc, Rcc means all condition code variants, i.e. JNZ, JZ, JNC, JC, JPO, JPE, JP, JM, etc.
String nonM1 or nonM2 means all registers but M as destination register, string nonM2 has an analogue meaning for source register.
The output from this ROM are 48 lines (decoded instructions). All 48 lines go to the right side where instruction timing ROM is. This ROM tells how long each instruction in cycles and clocks is. The content and explanation of this ROM can be found here.
Only 46 lines go to the left side where control signals for ALU and register file are created. The two signals which do not go to the left are for instructions DI, EI and HLT. The reason is that those instructions do not use ALU or change registers so their functionality is implemented in the right side of the chip.
In the table below bitmasks are shown. If a corresponding bit contains "x" it means that it is a don't-care bit. If there is a "+" sign it means that the corresponding bit is one of a don't-care triplet which may be anything but "110" (M1 or M2).

/INS_B2	INS_B2	/INS_B1	INS_B1	INS_B7	/INS_B7	/INS_B4	INS_B4	/INS_B5	INS_B5	INS_B3	/INS_B3	/INS_B0	INS_B0	/INS_B6	INS_B6	INS_M2	INS_M1	Bitmask	Instruction(s)
0	1	1	0	0	1	1	0	1	0	0	0	1	0	1	0	0	0	1111 x011	DI, EI
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	1	1	0	10xx x+++	ALU nonM2
1	0	1	0	0	1	0	0	0	0	0	0	0	1	1	0	0	0	11xx x110	ALU imm
0	1	0	1	1	0	0	0	1	0	1	0	0	1	0	1	0	0	001x 0000	RIM, SIM
1	0	1	0	0	1	0	0	0	0	0	0	0	1	0	1	0	0	10xx x110	ALU M
1	0	1	0	0	1	0	0	0	0	0	0	1	0	1	0	0	0	11xx x111	RST x
1	0	1	0	1	0	0	0	1	0	0	0	1	0	0	1	0	0	001x x111	DAA, CMA, STC, CMC
0	1	1	0	0	1	0	1	0	1	0	1	1	0	1	0	0	0	1100 1011	RSTV

0	1	1	0	1	0	1	0	1	0	1	0	0	1	0	1	0	0	0011 0010	STA
0	1	1	0	1	0	1	0	1	0	0	1	0	1	0	1	0	0	0011 1010	LDA
0	1	0	1	0	1	1	0	0	1	0	1	1	0	1	0	0	0	1101 1001	SHLX
1	0	0	1	0	1	0	1	1	0	0	1	1	0	1	0	0	0	1110 1101	LHLX
0	1	1	0	1	0	0	1	1	0	1	0	0	1	0	1	0	0	0010 0010	SHLD
0	1	1	0	1	0	0	1	1	0	0	1	0	1	0	1	0	0	0010 1010	LHLD
1	0	1	0	1	0	0	0	0	0	0	0	0	1	0	1	0	1	00++ +110	MVI nonM1
0	1	1	0	0	1	1	0	0	1	0	1	1	0	1	0	0	0	1101 1011	IN

1	0	1	0	1	0	1	0	1	0	1	0	0	1	0	1	0	0	0011 0110	MVI M
0	1	1	0	0	1	1	0	0	1	1	0	1	0	1	0	0	0	1101 0011	OUT
0	1	0	1	0	1	0	1	0	1	0	1	1	0	1	0	0	0	1100 1001	RET
0	1	0	1	0	1	0	0	0	0	0	0	0	1	1	0	0	0	11xx x000	Rcc
0	1	0	1	1	0	0	0	0	0	0	1	1	0	0	1	0	0	00xx 1001	DAD
0	1	0	1	1	0	0	1	0	1	0	1	0	1	0	1	0	0	0000 1000	DSUB
0	1	0	1	1	0	1	0	0	1	0	1	0	1	0	1	0	0	0001 1000	RDEL
0	1	0	1	1	0	0	0	1	0	0	1	0	1	0	1	0	0	001x 1000	LDHI, LDSI

0	1	0	1	1	0	1	0	0	1	1	0	0	1	0	1	0	0	0001 0000	ARHL
1	0	1	0	1	0	0	0	0	1	0	0	1	0	0	1	0	0	000x x111	RLC, RRC, RAL, RAR
1	0	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	11xx 0101	PUSH
0	1	0	1	0	1	0	0	0	0	1	0	1	0	1	0	0	0	11xx 0001	POP
0	1	0	1	0	1	1	0	1	0	0	1	1	0	1	0	0	0	1111 1001	SPHL
0	1	1	0	0	1	0	0	0	0	0	0	0	1	1	0	0	0	11xx x010	Jcc
0	1	1	0	0	1	0	1	0	1	1	0	1	0	1	0	0	0	1100 0011	JMP
1	0	0	1	0	1	1	0	0	0	0	1	1	0	1	0	0	0	11x1 1101	JNK, JK

0	1	0	1	0	1	0	1	1	0	0	1	1	0	1	0	0	0	1110 1001	PCHL
1	0	0	1	0	1	0	0	0	0	0	0	0	1	1	0	0	0	11xx x100	Ccc
1	0	0	1	0	1	0	1	0	1	0	1	1	0	1	0	0	0	1100 1101	CALL
0	1	1	0	0	1	0	1	1	0	1	0	1	0	1	0	0	0	1110 0011	XTHL
0	1	1	0	1	0	0	0	0	0	1	0	1	0	0	1	0	0	00xx 0011	INX
0	1	1	0	1	0	0	0	0	0	0	1	1	0	0	1	0	0	00xx 1011	DCX
1	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	1	00++ +10x	INR nonM1, DCR nonM1
1	0	0	1	1	0	1	0	1	0	1	0	0	0	0	1	0	0	0011 010x	INR M, DCR M

0	1	1	0	1	0	0	0	0	1	1	0	0	1	0	1	0	0	000x 0010	STAX
0	1	1	0	1	0	0	0	0	1	0	1	0	1	0	1	0	0	000x 1010	LDAX
0	1	0	1	1	0	0	0	0	0	1	0	1	0	0	1	0	0	00xx 0001	LXI
0	0	0	0	1	0	1	0	1	0	1	0	0	0	1	0	1	0	0111 0+++	MOV M,nonM2
1	0	1	0	1	0	0	0	0	0	0	0	0	1	1	0	0	1	01++ +110	MOV nonM1,M
0	0	0	0	1	0	0	0	0	0	0	0	0	0	1	0	1	1	01++ ++++	MOV nonM1,nonM2
0	1	1	0	0	1	0	1	1	0	0	1	1	0	1	0	0	0	1110 1011	XCHG
1	0	1	0	1	0	1	0	1	0	1	0	0	1	1	0	0	0	0111 0110	HLT