Intel 8085 instruction decode ROM
In my layers drawing instruction decode ROM occupies rectangle from 5263,1866 to 5712,3117. In the table below the content of the ROM is shown. Every 1 means a FET which can pull each line down. The table is in the same sequence as it is in the real chip.
Particular line is high when instruction register contains corresponding instruction. Every line contains NOR term meaning default value is logical 1. The ROM has 18 inputs. Every bit of instruction register and its negation (INS_B0, /INS_B0 ... INS_B7, /INS_B7)
and two additional signals used for decoding of M pseudoregister.
First is INS_M1 defined as NOR(/INS_B5,/INS_B4,INS_B3) i.e. is 1 for instructions xx110xxx and 0 otherwise. The second is INS_M2 and is defined as NOR(/INS_B2,/INS_B1,INS_B0) i.e. is 1 for instructions xxxxx110 and 0 otherwise.
Every pair of instruction bit and its negation can tell if corresponding bit should be 0, 1 or don't care. Note that there is no decode line for NOP instruction. The reason is that this instruction does not do anything specific.
Instruction register gets loaded during cycle M1, state T3, phase P1 and it is held there till M1, T2, P2 of the next instruction.
In the instruction list below ALU means all 8 ALU instructions (ADD, ADC, SUB, SBB, ANA, XRA, ORA, CMP) or their immediate version (ADI, ACI, SUI, SBI, ANI, XRI, ORI, CPI). String cc in Jcc, Ccc, Rcc means all condition code variants, i.e. JNZ, JZ, JNC, JC, JPO, JPE, JP, JM, etc.
String nonM1 or nonM2 means all registers but M as destination register, string nonM2 has an analogue meaning for source register.
The output from this ROM are 48 lines (decoded instructions). All 48 lines go to the right side where instruction timing ROM is. This ROM tells how long each instruction in cycles and clocks is. The content and explanation of this ROM can be found here.
Only 46 lines go to the left side where control signals for ALU and register file are created. The two signals which do not go to the left are for instructions DI, EI and HLT. The reason is that those instructions do not use ALU or change registers so their functionality is implemented in the right side of the chip.
|
|
|
|
| |
|
|
|
| |
|
|
|
| |
|
|
|
| |
|
| | |
| 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | DI, EI |
| 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | | 1 | 0 | | ALU nonM2 |
| 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | | ALU imm |
| 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | RIM, SIM |
| 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | ALU M |
| 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | RST x |
| 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | | 0 | 0 | | DAA, CMA, STC, CMC |
| 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | RSTV |
|
| 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | STA |
| 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | LDA |
| 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | SHLX |
| 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | LHLX |
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | SHLD |
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | LHLD |
| 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | | MVI nonM1 |
| 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | IN |
|
| 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | MVI M |
| 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | OUT |
| 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | RET |
| 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | | Rcc |
| 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | | 0 | 0 | | DAD |
| 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | DSUB |
| 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | RDEL |
| 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 | | 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | LDHI, LDSI |
|
| 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | ARHL |
| 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 0 | | 1 | 0 | 0 | 1 | | 0 | 0 | | RLC, RRC, RAL, RAR |
| 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | PUSH |
| 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 0 | | 0 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | POP |
| 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | SPHL |
| 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | | Jcc |
| 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | JMP |
| 1 | 0 | 0 | 1 | | 0 | 1 | 1 | 0 | | 0 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | JNK, JK |
|
| 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | PCHL |
| 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | | Ccc |
| 1 | 0 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | CALL |
| 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | | XTHL |
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 1 | 0 | 0 | 1 | | 0 | 0 | | INX |
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | | 1 | 0 | 0 | 1 | | 0 | 0 | | DCX |
| 1 | 0 | 0 | 1 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 0 | 0 | 1 | | 0 | 1 | | INR nonM1, DCR nonM1 |
| 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | 0 | 1 | | 0 | 0 | | INR M, DCR M |
|
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 0 | 0 | | STAX |
| 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | | 0 | 1 | 0 | 1 | | 0 | 0 | | LDAX |
| 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 1 | 0 | 0 | 1 | | 0 | 0 | | LXI |
| 0 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 0 | 1 | 0 | | 1 | 0 | | MOV M,nonM2 |
| 1 | 0 | 1 | 0 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 0 | 1 | | MOV nonM1,M |
| 0 | 0 | 0 | 0 | | 1 | 0 | 0 | 0 | | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 1 | 1 | | MOV nonM1,nonM2 |
| 0 | 1 | 1 | 0 | | 0 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | | 1 | 0 | 1 | 0 | | 0 | 0 | | XCHG |
| 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 1 | 0 | 1 | 0 | | 0 | 1 | 1 | 0 | | 0 | 0 | | HLT |