Intel 8085 instruction decode ROM

In my layers drawing instruction decode ROM occupies rectangle from 5263,1866 to 5712,3117. In the table below the content of the ROM is shown. Every 1 means a FET which can pull each line down. The table is in the same sequence as it is in the real chip.
Particular line is high when instruction register contains corresponding instruction. Every line contains NOR term meaning default value is logical 1. The ROM has 18 inputs. Every bit of instruction register and its negation (INS_B0, /INS_B0 ... INS_B7, /INS_B7) and two additional signals used for decoding of M pseudoregister.
First is INS_M1 defined as NOR(/INS_B5,/INS_B4,INS_B3) i.e. is 1 for instructions xx110xxx and 0 otherwise. The second is INS_M2 and is defined as NOR(/INS_B2,/INS_B1,INS_B0) i.e. is 1 for instructions xxxxx110 and 0 otherwise.
Every pair of instruction bit and its negation can tell if corresponding bit should be 0, 1 or don't care. Note that there is no decode line for NOP instruction. The reason is that this instruction does not do anything specific.
Instruction register gets loaded during cycle M1, state T3, phase P1 and it is held there till M1, T2, P2 of the next instruction.
In the instruction list below ALU means all 8 ALU instructions (ADD, ADC, SUB, SBB, ANA, XRA, ORA, CMP) or their immediate version (ADI, ACI, SUI, SBI, ANI, XRI, ORI, CPI). String cc in Jcc, Ccc, Rcc means all condition code variants, i.e. JNZ, JZ, JNC, JC, JPO, JPE, JP, JM, etc.
String nonM1 or nonM2 means all registers but M as destination register, string nonM2 has an analogue meaning for source register.
The output from this ROM are 48 lines (decoded instructions). All 48 lines go to the right side where instruction timing ROM is. This ROM tells how long each instruction in cycles and clocks is. The content and explanation of this ROM can be found here.
Only 46 lines go to the left side where control signals for ALU and register file are created. The two signals which do not go to the left are for instructions DI, EI and HLT. The reason is that those instructions do not use ALU or change registers so their functionality is implemented in the right side of the chip.
/INS_B2
INS_B2
/INS_B1
INS_B1
 
INS_B7
/INS_B7
/INS_B4
INS_B4
 
/INS_B5
INS_B5
INS_B3
/INS_B3
 
/INS_B0
INS_B0
/INS_B6
INS_B6
 
INS_M2
INS_M1
 
0110 0110 1000 1010 00 DI, EI
0000 0100 0000 0001 10 ALU nonM2
1010 0100 0000 0110 00 ALU imm
0101 1000 1010 0101 00 RIM, SIM
1010 0100 0000 0101 00 ALU M
1010 0100 0000 1010 00 RST x
1010 1000 1000 1001 00 DAA, CMA, STC, CMC
0110 0101 0101 1010 00 RSTV
0110 1010 1010 0101 00 STA
0110 1010 1001 0101 00 LDA
0101 0110 0101 1010 00 SHLX
1001 0101 1001 1010 00 LHLX
0110 1001 1010 0101 00 SHLD
0110 1001 1001 0101 00 LHLD
1010 1000 0000 0101 01 MVI nonM1
0110 0110 0101 1010 00 IN
1010 1010 1010 0101 00 MVI M
0110 0110 0110 1010 00 OUT
0101 0101 0101 1010 00 RET
0101 0100 0000 0110 00 Rcc
0101 1000 0001 1001 00 DAD
0101 1001 0101 0101 00 DSUB
0101 1010 0101 0101 00 RDEL
0101 1000 1001 0101 00 LDHI, LDSI
0101 1010 0110 0101 00 ARHL
1010 1000 0100 1001 00 RLC, RRC, RAL, RAR
1001 0100 0010 1010 00 PUSH
0101 0100 0010 1010 00 POP
0101 0110 1001 1010 00 SPHL
0110 0100 0000 0110 00 Jcc
0110 0101 0110 1010 00 JMP
1001 0110 0001 1010 00 JNK, JK
0101 0101 1001 1010 00 PCHL
1001 0100 0000 0110 00 Ccc
1001 0101 0101 1010 00 CALL
0110 0101 1010 1010 00 XTHL
0110 1000 0010 1001 00 INX
0110 1000 0001 1001 00 DCX
1001 1000 0000 0001 01 INR nonM1, DCR nonM1
1001 1010 1010 0001 00 INR M, DCR M
0110 1000 0110 0101 00 STAX
0110 1000 0101 0101 00 LDAX
0101 1000 0010 1001 00 LXI
0000 1010 1010 0010 10 MOV M,nonM2
1010 1000 0000 0110 01 MOV nonM1,M
0000 1000 0000 0010 11 MOV nonM1,nonM2
0110 0101 1001 1010 00 XCHG
1010 1010 1010 0110 00 HLT