Intel 8085 Register Control ROM

Intel 8085 register control ROM

In my layers drawing register timing ROM occupies rectangle from 3462,3580 to 5287,4189. In the table below the content of the ROM is shown. Every 1 means a FET which can pull each line down. The table is in the same sequence as it is in the real chip.
There are 58 inputs to the ROM comming from the top (from the register timing ROM). Each input is high when particular instruction group and time are active.
There are 19 outputs from the table, physically going out to the left side. The outputs are passed thru PHI1 so that they are aligned with real T* states (don't forget that all CYC_* and T* signals are one phase ahead) and the result is negated because ROM is created from NORs as usually.
From this it is obvious that this ROM is OR plane of 8085's PLA.
Not all the signals have its names yet, I'll name them after I discover their functionality and they appear in the schematic section.
The lower table is a summary of instruction groups / instruction timing groups when each signal occures (i.e. is low before negating or high thereafter).

Register timing group	01	02	03	04	05	06	07	08	09	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34	35	36	37	38	39	40	41	42	43	44	45	46	47	48	49	50	51	52	53	54	55	56	57	58
???_01	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0
NO_DREG_WR	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
???_03	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0
???_04	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0
???_05	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0
???_06	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
???_07	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
???_08	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0
???_09	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0	1	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0
???_10	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
REG_PC_RWa	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	1	0	0	0	0	0	0	0	0	0	1	1	1	0	0	0	0	0	0	0
???_12	0	0	0	0	0	1	1	1	0	0	0	0	0	0	0	0	1	0	0	0	1	0	0	0	0	0	0	0	1	1	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
WZ_NOT_PC	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0
REG2_RD	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0
SWP_DE_HL	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0
DREG_CNT2	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
/DREG_CNTa	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
DREG_DECa	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0
NO_DREG_RW	0	0	0	0	0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Signal	Group	Group	Instructions	Timing
???_01	03	07	ARHL	R1T1
	04	09	DAD, DSUB, RDEL, LDHI, LDSI	R2T2T3
	19	23	RST, RSTV, PUSH, Ccc, CALL, XTHL	W1T1
	39	46	SHLX, SHLD	W2T1
NO_DREG_WR	02	04	RSTV, Rcc, Jcc, JNK, JK, Ccc	M1T5
???_03	06	13	ALU nonM2, DAA, CMA, STC, CMC, RLC, RRC, RAL, RAR, INR nonM1, DCR nonM1, MOV nonM1,nonM2	M1T1
???_03	50	56	ALU nonM2, DAA, CMA, STC, CMC, RLC, RRC, RAL, RAR, MOV M,nonM2, MOV nonM1,nonM2	W1T1
???_04	04	10	DAD, DSUB, RDEL, LDHI, LDSI	R1
	19	24	RST, RSTV, PUSH, Ccc, CALL, XTHL	W2T1
	24	31	ARHL, XTHL	M1T1
	39	45	SHLX, SHLD	W1T1
???_05	40	47	MVI nonM1, POP, INR nonM1, DCR nonM1, MOV nonM1,M, MOV nonM1,nonM2	M1T3
???_06	--	01	All instructions	R2T1
	09	16	IN, OUT	R2T3
	24	29	ARHL, XTHL	M1T3
	27	34	LHLD	W2T2
	30	36	RST, RSTV	W2T3
???_07	03	06	ARHL	R1T3
	19	25	RST, RSTV, PUSH, Ccc, CALL, XTHL	W2T2
	25	32	STA, LDA, SHLD, LHLD, IN, OUT, RET, Rcc, Jcc, JMP, JNK, JK	R2T3
	26	33	LHLX, LHLD, DAD, DSUB, RDEL, LDHI, LDSI, LXI	M1T3
???_08	08	14	RET, Rcc, POP, XTHL	R1T3, R2T2
	08	15	RET, Rcc, POP, XTHL	M1T4, R1T2
	19	26	RST, RSTV, PUSH, Ccc, CALL, XTHL	M1T4T5, R2T3, W1T2T3
	34	41	RST, RSTV, Rcc, PUSH	M1T6
	48	55	SPHL	M1T5
???_09	04	12	DAD, DSUB, RDEL, LDHI, LDSI	R2T1T2
	06	13	ALU nonM2, DAA, CMA, STC, CMC, RLC, RRC, RAL, RAR, INR nonM1, DCR nonM1, MOV nonM1,nonM2	M1T1
	11	18	RDEL, LDHI, LDSI	R2T3
	11	19	RDEL, LDHI, LDSI	R1T1
	20	27	PUSH, MOV M,nonM2	M1T3, W1T1, W2T1
	28	35	LHLX, MVI nonM1, POP, INR nonM1, DCR nonM1, LXI, MOV nonM1,M, MOV nonM1,nonM2	M1T3, R2T1
	35	43	DAD, DSUB, RDEL, ARHL	R1T2
	37	44	INX, DCX, STAX, LDAX	M1T4T5
???_10	11	20	RDEL, LDHI, LDSI	M1T3, R2T1
???_10	31	38	SHLX, LHLX	M1T4
REG_PC_RWa	--	02	All instructions	M1T2
	30	37	RST, RSTV	M1T3, W1T1, W2T1
	32	39	PCHL	M1T5
	42	49	Ccc, CALL	M1T6, R1T2, W1T1, W2T1
	43	50	STA, LDA, SHLD, LHLD, IN, MVI M, OUT, DAD, DSUB, RDEL, LDHI, LDSI, Jcc, JMP, JNK, JK, Ccc, CALL, LXI	R1T3, R2T2
	44	51	ALU imm, STA, LDA, SHLD, LHLD, MVI nonM1, IN, MVI M, OUT, DAD, DSUB, RDEL, LDHI, LDSI, ARHL, Jcc, JMP, JNK, JK, LXI	M1T4, R1T2
???_12	03	06	ARHL	R1T3
	03	07	ARHL	R1T1
	03	08	ARHL	M1T1
	10	17	MVI M, INR M, DCR M	R2T3
	15	21	ALU M, SPHL, PCHL, INR M, DCR M, MOV M,nonM2, MOV nonM1,M	M1T4
	24	29	ARHL, XTHL	M1T3
	24	30	ARHL, XTHL	W2T2
	27	34	LHLD	W2T2
	33	40	SHLX, SHLD, LHLD, DAD, DSUB, XTHL	M1T3, W1T1, W2T1
	51	58	DAD, DSUB	R1T1, R2T3
WZ_NOT_PC	02	03	RSTV, Rcc, Jcc, JNK, JK, Ccc	FLAG_MET
WZ_NOT_PC	45	52	RST, RET, JMP, CALL	All the time
REG2_RD	50	57	ALU nonM2, DAA, CMA, STC, CMC, RLC, RRC, RAL, RAR, MOV M,nonM2, MOV nonM1,nonM2	M1T4
SWP_DE_HL	41	48	XCHG	M1T1
DREG_CNT2	02	05	RSTV, Rcc, Jcc, JNK, JK, Ccc	R1T1T2
/DREG_CNTa	15	22	ALU M, SPHL, PCHL, INR M, DCR M, MOV M,nonM2, MOV nonM1,M	M1T4T5
/DREG_CNTa	24	28	ARHL, XTHL	R2T1T2
DREG_DECa	47	53	RST, RSTV, PUSH, Ccc, CALL, XTHL, DCX	W1T1T2
DREG_DECa	47	54	RST, RSTV, PUSH, Ccc, CALL, XTHL, DCX	M1T4T5
NO_DREG_RW	03	06	ARHL	R1T3
	04	11	DAD, DSUB, RDEL, LDHI, LDSI	R2
	35	43	DAD, DSUB, RDEL, ARHL	R1T2