65CE02 instruction set

  x0  x1  x2  x3  x4  x5  x6  x7  x8  x9  xA  xB  xC  xD  xE  xF 
 0x BRK
2     7
----I--		ORA (a8,X)
2     5
N----Z-		CLE
1     2
--E----		SEE
1     2
--E----		TSB a8
2     4
-----Z-		ORA a8
2     3
N----Z-		ASL a8
2     4
N----ZC		RMB0 a8
2     4
-------		PHP
1     3
-------		ORA #d8
2     2
N----Z-		ASL A
1     1
N----ZC		TSY
1     1
N----Z-		TSB a16
3     5
-----Z-		ORA a16
3     4
N----Z-		ASL a16
3     5
N----ZC		BBR0 a8,r8
3     4
-------
 1x BPL r8
2     2
-------		ORA (a8),Y
2     5
N----Z-		ORA (a8),Z
2     5
N----Z-		BPL r16
3     3
-------		TRB a8
2     4
-----Z-		ORA a8,X
2     3
N----Z-		ASL a8,X
2     4
N----ZC		RMB1 a8
2     4
-------		CLC
1     1
------C		ORA a16,Y
3     4
N----Z-		INC A
1     1
N----Z-		INZ
1     1
N----Z-		TRB a16
3     5
-----Z-		ORA a16,X
3     4
N----Z-		ASL a16,X
3     5
N----ZC		BBR1 a8,r8
3     4
-------
 2x JSR a16
3     5
-------		AND (a8,X)
2     5
N----Z-		JSR (a16)
3     7
-------		JSR (a16,X)
3     7
-------		BIT a8
2     3
NV---Z-		AND a8
2     3
N----Z-		ROL a8
2     4
N----ZC		RMB2 a8
2     4
-------		PLP
1     3
NV-DIZC		AND #d8
2     2
N----Z-		ROL A
1     1
N----ZC		TYS
1     1
-------		 BIT a16
3     4
NV---Z-		AND a16
3     4
N----Z-		ROL a16
3     5
N----ZC		BBR2 a8,r8
3     4
-------
 3x BMI r8
2     2
-------		AND (a8),Y
2     5
N----Z-		AND (a8),Z
2     5
N----Z-		BMI r16
3     3
-------		BIT a8,X
2     3
NV---Z-		AND a8,X
2     3
N----Z-		ROL a8,X
2     4
N----ZC		RMB3 a8
2     4
-------		SEC
1     1
------C		AND a16,Y
3     4
N----Z-		DEC A
1     1
N----Z-		DEZ
1     1
N----Z-		 BIT a16,X
3     4
NV---Z-		AND a16,X
3     4
N----Z-		ROL a16,X
3     5
N----ZC		BBR3 a8,r8
3     4
-------
 4x RTI
1     5
NV-DIZC		EOR (a8,X)
2     5
N----Z-		NEG A
1     2
N----Z-		ASR A
1     2
N----ZC		ASR a8
2     4
N----ZC		EOR a8
2     3
N----Z-		LSR a8
2     4
N----ZC		RMB4 a8
2     4
-------		PHA
1     3
-------		EOR #d8
2     2
N----Z-		LSR A
1     1
N----ZC		TAZ
1     1
N----Z-		JMP a16
3     3
-------		EOR a16
3     4
N----Z-		LSR a16
3     5
N----ZC		BBR4 a8,r8
3     4
-------
 5x BVC r8
2     2
-------		EOR (a8),Y
2     5
N----Z-		EOR (a8),Z
2     5
N----Z-		BVC r16
3     3
-------		ASR a8,X
2     4
N----ZC		EOR a8,X
2     3
N----Z-		LSR a8,X
2     4
N----ZC		RMB5 a8
2     4
-------		CLI
1     2
----I--		EOR a16,Y
3     4
N----Z-		PHY
1     3
-------		TAB
1     1
-------		AUG
4     4
-------		EOR a16,X
3     4
N----Z-		LSR a16,X
3     5
N----ZC		BBR5 a8,r8
3     4
-------
 6x RTS
1     4
-------		ADC (a8,X)
2     5
NV---ZC		RTN #d8
2     7
-------		BSR r16
3     5
-------		STZ a8
2     3
-------		ADC a8
2     3
NV---ZC		ROR a8
2     4
N----ZC		RMB6 a8
2     4
-------		PLA
1     3
N----Z-		ADC #d8
2     2
NV---ZC		ROR A
1     1
N----ZC		TZA
1     1
N----Z-		JMP (a16)
3     5
-------		ADC a16
3     4
NV---ZC		ROR a16
3     5
N----ZC		BBR6 a8,r8
3     4
-------
 7x BVS r8
2     2
-------		ADC (a8),Y
2     5
NV---ZC		ADC (a8),Z
2     5
NV---ZC		BVS r16
3     3
-------		STZ a8,X
2     3
-------		ADC a8,X
2     3
NV---ZC		ROR a8,X
2     4
N----ZC		RMB7 a8
2     4
-------		SEI
1     2
----I--		ADC a16,Y
3     4
NV---ZC		PLY
1     3
N----Z-		TBA
1     1
N----Z-		JMP (a16,X)
3     5
-------		ADC a16,X
3     4
NV---ZC		ROR a16,X
3     5
N----ZC		BBR7 a8,r8
3     4
-------
 8x BRU r8
2     2
-------		STA (a8,X)
2     5
-------		STA (r8,SP),Y
2     6
-------		BRU r16
3     3
-------		STY a8
2     3
-------		STA a8
2     3
-------		STX a8
2     3
-------		SMB0 a8
2     4
-------		DEY
1     1
N----Z-		BIT #d8
2     2
NV---Z-		TXA
1     1
N----Z-		STY a16,X
3     4
-------		STY a16
3     4
-------		STA a16
3     4
-------		STX a16
3     4
-------		BBS0 a8,r8
3     4
-------
 9x BCC r8
2     2
-------		STA (a8),Y
2     5
-------		STA (a8),Z
2     5
-------		BCC r16
3     3
-------		STY a8,X
2     3
-------		STA a8,X
2     3
-------		STX a8,Y
2     3
-------		SMB1 a8
2     4
-------		TYA
1     1
N----Z-		STA a16,Y
3     4
-------		TXS
1     1
-------		STX a16,Y
3     4
-------		STZ a16
3     4
-------		STA a16,X
3     4
-------		STZ a16,X
3     4
-------		BBS1 a8,r8
3     4
-------
 Ax LDY #d8
2     2
N----Z-		LDA (a8,X)
2     5
N----Z-		LDX #d8
2     2
N----Z-		LDZ #d8
2     2
N----Z-		LDY a8
2     3
N----Z-		LDA a8
2     3
N----Z-		LDX a8
2     3
N----Z-		SMB2 a8
2     4
-------		TAY
1     1
N----Z-		LDA #d8
2     2
N----Z-		TAX
1     1
N----Z-		LDZ a16
3     4
N----Z-		LDY a16
3     4
N----Z-		LDA a16
3     4
N----Z-		LDX a16
3     4
N----Z-		BBS2 a8,r8
3     4
-------
 Bx BCS r8
2     2
-------		LDA (a8),Y
2     5
N----Z-		LDA (a8),Z
2     5
N----Z-		BCS r16
3     3
-------		LDY a8,X
2     3
N----Z-		LDA a8,X
2     3
N----Z-		LDX a8,Y
2     3
N----Z-		SMB3 a8
2     4
-------		CLV
1     1
-V-----		LDA a16,Y
3     4
N----Z-		TSX
1     1
N----Z-		LDZ a16,X
3     4
N----Z-		LDY a16,X
3     4
N----Z-		LDA a16,X
3     4
N----Z-		LDX a16,Y
3     4
N----Z-		BBS3 a8,r8
3     4
-------
 Cx CPY #d8
2     2
N----ZC		CMP (a8,X)
2     5
N----ZC		CPZ #d8
2     2
N----ZC		DEW a8
2     6
N----Z-		CPY a8
2     3
N----ZC		CMP a8
2     3
N----ZC		DEC a8
2     4
N----Z-		SMB4 a8
2     4
-------		INY
1     1
N----Z-		CMP #d8
2     2
N----ZC		DEX
1     1
N----Z-		ASW a16
3     7
N----ZC		CPY a16
3     4
N----ZC		CMP a16
3     4
N----ZC		DEC a16
3     5
N----Z-		BBS4 a8,r8
3     4
-------
 Dx BNE r8
2     2
-------		CMP (a8),Y
2     5
N----ZC		CMP (a8),Z
2     5
N----ZC		BNE r16
3     3
-------		CPZ a8
2     3
N----ZC		CMP a8,X
2     3
N----ZC		DEC a8,X
2     4
N----Z-		SMB5 a8
2     4
-------		CLD
1     1
---D---		CMP a16,Y
3     4
N----ZC		PHX
1     3
-------		PHZ
1     3
-------		CPZ a16
3     4
N----ZC		CMP a16,X
3     4
N----ZC		DEC a16,X
3     5
N----Z-		BBS5 a8,r8
3     4
-------
 Ex CPX #d8
2     2
N----ZC		SBC (a8,X)
2     5
NV---ZC		LDA (r8,SP),Y
2     6
N-----Z-		INW a8
2     6
N----Z-		CPX a8
2     3
N----ZC		SBC a8
2     3
NV---ZC		INC a8
2     4
N----Z-		SMB6 a8
2     4
-------		INX
1     1
N----Z-		SBC #d8
2     2
NV---ZC		NOP
1     1
-------		ROW a16
3     7
N----ZC		CPX a16
3     4
N----ZC		SBC a16
3     4
NV---ZC		INC a16
3     5
N----Z-		BBS6 a8,r8
3     4
-------
 Fx BEQ r8
2     2
-------		SBC (a8),Y
2     5
NV---ZC		SBC (a8),Z
2     5
NV---ZC		BEQ r16
3     3
-------		PHW #d16
3     5
-------		SBC a8,X
2     3
NV---ZC		INC a8,X
2     4
N----Z-		SMB7 a8
2     4
-------		SED
1     1
---D---		SBC a16,Y
3     4
NV---ZC		PLX
1     3
N----Z-		PLZ
1     3
N----Z-		PHW a16
3     7
-------		SBC a16,X
3     4
NV---ZC		INC a16,X
3     5
N----Z-		BBS7 a8,r8
3     4
-------


       Misc/control instructions
       Jumps/branches/calls
       Load/store/transfer instructions
       Arithmetic/logical instructions
       Shift/rotation/bit instructions
  
 
Length in bytes →
 		   INS a8
2     3
NVEDIZC		   ← Instruction mnemonic
← Duration in cycles
← Flags affected
  B flag does not exist physically, so cannot be modified.
E flag (disable extended stack operation) cannot be from obvious reasons changed by PLP or RTI instruction. TYS and TSY work even if flag E is set.
BBR and BBS instructions are both bit and branch instructions.

Flags affected are always shown in N V E D I Z C order. If it is marked by "-" it is not changed. If it is marked by "N", "V", "E", "D", "I", "Z" or "C" corresponding flag is affected by particular instruction. B flag is not mentioned here.

#d8  means immediate 8 bit data
#d16 means immediate 16 bit data
a8   means 8 bit address (base page)
a16  means 16 bit address
r8   means 8 bit signed data, which are added to program counter or stack pointer
r16  means 16 bit signed data, which are added to program counter


Registers
 7  .  .  .  .  .  0
 A - accumulator
 X - index register
 Y - index register
 Z - index register
 B - base page
 
 
 
 
 

15  .  .  .  .  .  .  .  .  .  .  .  .  .  0
SP (SPH/SPL) - stack pointer
PC (PCH/PCL) - program counter



   Processor status register (P) bits:

7 6 5 4 3 2 1 0
N V E B D I Z C

N - Negative Flag
V - Overflow Flag
E - Stack Extend Disabled
B - Break Executed
D - Decimal Mode Enabled
I - Interrupt Disabled
Z - Zero Flag
C - Carry Flag